TB9051FTG simplified truth table (PWM1 + PWM2 + EN)

Hey,
in the description for the TB9051FTG are two different ways of controlling the motor shown. The version with EN set to High and either pwm1 or pwm2 is pwm driven. This version works fine for me. But as I have only few pwm pins available, the second version seems more suiting. So Pwm1 is set high and pwm2 is set low. Then enb is set low and EN is used to drive the speed of the motor using pwm. The behaviour of the motor is: either it is not moving or it is moving as fast as possible.
Am I missing something?
Thanks

Hey,
just wondering if the TB9051FTG has cmos or TTL logic.
Thanks

I merged your posts because they are about the same product. The datasheet for the TB9051FTG describes it as CMOS. You can find the datasheet for that motor driver under the Resources tab of its product page.

As for the PWM1 + PWM2 + EN control scheme, when EN is driven high the output behavior is driving forward at the duty cycle of the PWM signal (which could be as fast as possible if you are using a 100% duty cycle). When EN is held low, the outputs are high-impedance (this is usually denoted by ā€˜Zā€™ in truth tables like the ones we use), which means that the motor is coasting.

-Jon

Thanks,
alright, but when I am inbetween high and low with the pwm on the en pin, nothing happens. So it cant really be used for pwm usage?

Oh and as it is cmos, is it possible to drive it on a 3.3V level?

Hi, jacko91.

I did some more testing on one of these drivers, and it looks like there are actually some timing restrictions that make it impractical to use high-frequency PWM on the enable pins (EN or ENB). Specifically, I observed that the TB9051FTG seems to have a minimum off-time of about 80 microseconds when its outputs are turned off with EN or ENB. This means that PWM frequencies above a few kHz are mostly impractical, and it puts a limit on the maximum achievable duty cycle. (For example, at 1.25 kHz, each PWM period has a length of 800 us; if the outputs are off for 80 us minimum, the maximum achievable duty cycle is 90%.)

I suspect you are seeing strange behavior because you are using a higher frequency PWM signal. If using a lower frequency is an option for you, could you try to see if it works better? We will work on updating the product page for the board to make this limitation clear.

The driver should work fine with 3.3 V logic signals (the logic high threshold for its inputs is 1.75 V).

Kevin

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