I have a setup running (currently) one Tic Controller using serial transmission. I have a Raspi 3+ running Python and everything is working fine. I went the serial route, instead of i2c, because I have to transmit the commands a bit further than is suggested for i2c.
I am running at 9600 baud, but have also tested 115K without issues.
As indicated in the Tic manual, I will need an AND gate to get reliable communication from multiple Tic controllers. I know there are many logic chips available, but as a general guide, is there a suggested chip, or operational specs. one should use for selection?
Furthermore, can the AND Gate chips be cascaded?, i.e. I see some chips with 4 inputs and one output that run in the 3-5V VCC range. TI has a chip (SN54HC21)that is in a DIP pkg, so I can easily breadboard it. Since I am looking at controlling 24 stepper motors, it would seems I would need to have 6 chips (6 x 4 = 24) outputting into a set of two chips which then feed a third chip to get the 24 signals down to one going into the Raspi. I think looking at the datasheet for the chip, I may need to hold the unused 4th input HI on the second set of two chips.
I’m not looking for anyone to do the work for me, so to speak, just wanted to make sure I am not going down an incorrect path. This is not my area of expertise.