S18V20F12 SEPIC topology clarification


I’d like to request clarification on the operation of the S18V20F12 step-up/step-down voltage regulator. The product page notes the ENABLE pin can be driven low to place the board into a low-power state (~10 uA/V). However, it goes on to say:

Note that the SEPIC topology has an inherent capacitor from input to output; therefore, the output is not completely disconnected from the input even when the regulator is shut down.

Could you please explain what exactly this means? My intention is to use this step-up/down regulator to provide a constant 12 V voltage source when connected to a standard 12 V lead-acid battery (which can vary between 11-14 V). When ENABLE is driven low, I require that the load be completely disconnected. Otherwise, it will continue to consume power and result in a significant quiescent draw.


Hi, Adam.

The enable input on the S18V20F12 will turn off power to the regulator’s output leaving a current draw of only 10 to 20 µA per volt on VIN. The input and output of a SEPIC converter are connected by a capacitor so, as the regulator’s product page sates, they are not fully disconnected when the regulator is off. However, since capacitors do not conduct DC (steady-state) current, it should not have much effect on the current draw when the regulator is off and not switching, and I do not expect most users to have to worry about it. If you want to learn more about SEPIC topology, this wiki article is a good place to start.