I do not have a scope, this is the working example
#define F_CPU 20000000UL // Baby Orangutan frequency (20MHz)
#include <avr/io.h>
#define CE_LOW PORTB &= ~( 1 << PB5 ) // Define display port status
#define CE_HIGH PORTB |= ( 1 << PB5 )
#define DATA_LOW PORTD &= ~( 1 << PD1 )
#define DATA_HIGH PORTD |= ( 1 << PD1 )
#define RS_LOW PORTD &= ~( 1 << PD2 )
#define RS_HIGH PORTD |= ( 1 << PD2 )
#define CLK_LOW PORTD &= ~( 1 << PD4 )
#define CLK_HIGH PORTD |= ( 1 << PD4 )
int main (void)
{
DDRB |= 1 << PB0; PORTB |= ( 1 << PB0 );
DDRB |= 1 << PB5;
DDRD |= 1 << PD1;
DDRD |= 1 << PD2;
DDRD |= 1 << PD4;
RS_LOW; // Start value
CE_HIGH; // Start value
//*** setup display
RS_HIGH; // First RS is brought to logic high
CE_LOW; // and then CE is brought to logic low
// ******************************* Load control word0 01001111
CLK_LOW; // Low again
DATA_LOW; // 0 Controlword 0, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_HIGH; // 1 normal operation, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_LOW; // 0 brightness, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_LOW; // 0 brightness, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_HIGH; // 1 pwm, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_HIGH; // 1 pwm, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_HIGH; // 1 pwm, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_HIGH; // 1 pwm, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CE_HIGH; // when 8 bits have been loaded the CE line is brought to high
CLK_LOW; // when CLK goes to logic low, new dat is copied
// Load control word 1 10000001
RS_HIGH; // First RS is brought to logic high
CE_LOW; // and then CE is brought to logic low
CLK_LOW; // Low again
DATA_HIGH; // 1 Controlword 1, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_LOW; // 0, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_LOW; // 0, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_LOW; // 0, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_LOW; // 0, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_LOW; // 0, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_LOW; // 0, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low again
DATA_HIGH; // 1 Serial, next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CE_HIGH; // when 8 bits have been loaded the CE line is brought to high
CLK_LOW; // when CLK goes to logic low, new dat is copied
//*** end setup displsy
//*** begin zebra
RS_LOW; // First RS is brought low
CE_LOW; // then CE is brought low
unsigned int i;
for (i=1;i<=80;i++) // data entry, for test write 80 times 00, 01, 10 or 11 total bits 160
{
CLK_LOW; // Low again
DATA_LOW; // Next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next rising CLK edge
CLK_LOW; // Low ready to rise
DATA_HIGH; // Next each successive rising CLK edge will shift the data at the DIN pin
CLK_HIGH; // Next CLK rising edge
}
CE_HIGH; // When all 160 bits have been loaded CE is brought to logic high
CLK_LOW; // When CLK is next brought low, new data is latched into the dot drivers
//*** end zebra, all uneven dots should be off
return 0;
}